In September 2026, I began a Research Intern role in Embedded AI at Lab-STICC, IMT Atlantique, in Brest, France, through the France-Ghana FEF-AI4SD project.
I am developing MLPARE-Com, an integrated machine learning framework for joint physical- and link-layer optimization. It combines learned transceiver models, hybrid channel estimation algorithms, and Q-learning-driven retransmission policies.
The embedded testbed uses ESP32-S3 firmware for neural inference, real-time channel sensing, and adaptive ACK/NACK-based reliability control. The evaluation pipeline spans MIMO channel simulation, model training, embedded deployment, and analysis of communication reliability, latency, and computational performance. This work is supervised by Professor Derek Asiedu.